1. Field of the Invention
The present invention relates generally to built-in self-testing of logic (LBIST), and more particularly, to an apparatus and a method for improving observability and maintaining the validity of test coverage for a scan design in an integrated circuit environment.
2. Relevant Technology
Many Integrated Circuit (IC) logic circuit designs commonly include decoder outputs in electrical communication with state elements, such as latches or flip-flops. The state elements of the IC may in turn be in electrical communication with the select lines of a passgate multiplexer. Logic Circuit designs may employ a full scan design that advantageously provides controllability and observability of the internal logic in a circuit. For circuit designs that employ scanning, the state elements are usually scannable.
Built-in self testing of logic (LBIST) is a signature-based test methodology which depends on deterministic results. At any given time during the test, the test responses must be known and are compressed into a special structure such as a multiple input shift register (MISR) to produce a unique signature. A problem with LBIST is that a full scan may be unsafe for non-random state elements. During a full scan, scannable state elements receive random data from a pseudo random pattern generator (PRPG). However, in some circuit designs, certain state elements (non-random state elements) cannot tolerate random data and will not provide valid values.
One solution to scanning circuits having one or more non-random state elements is to operate a partial scan for the circuit. In a partial scan, the PRPG provides random data to the state elements except for the non-random state elements. This avoids the above noted problems, but converting a portion of the circuit into a non-scan mode during a LBIST may prove detrimental. This is because some intermediate stages having non-random state elements lack controllability and observability, which results in poor test coverage.
A further concern during a LBIST is the validity of the bit values supplied to passgate or transmission gate multiplexers. During general circuit operation, a circuit design with a multiplexer operates according to rules that ensure that the select lines of the multiplexer are always orthogonal, i.e., only one of the select lines is on. However, under test conditions, e.g., during a LBIST, the select lines may be driven by scannable state elements that receive random data that no longer abides by the orthogonal rule.
Another concern during LBIST arises from the fact that scannable state elements in the functional paths may receive random data that results in invalid outputs. For high performance in circuit design, the complex operation of decoding a wide bus during normal circuit operation may be carried over a number of clock cycles. When a full scan design is employed, partially decoded bit values are stored in the scannable state elements. Under system operation, this configuration works satisfactorily since the above scenario can be described as a functional path. However, under test conditions such as a LBIST, the scannable state elements in the functional path receive random data which no longer abide rules. As a result, invalid input values may be introduced to logic devices and in particular, the last stage of the functional path may no longer produce the desired result such as an orthogonal result (1-hot or 1-cold). If the logic devices receiving output from the last stage of the pipeline are combinational, then this poses no problem. However, if the last stage of the pipeline outputs to a 1-hot multiplexer that requires one and only one select line to be on, then the 1-hot multiplexer output will be invalid, which may destroy the validity of the LBIST. For example, if no select lines are on (0-hot), the multiplexer output will be floating which results in a high current state that could be detrimental to integrated circuit reliability. Having multiple select lines on could cause contention that has a similar effect to the 0-hot case.
It would therefore be an advancement in the art to ensure a 1-hot condition during LBIST for a multi-cycle decoded 1-hot multiplexor. Ensuring a 1-hot condition would avoid problems associated with an unknown value and provide validity of the LBIST. It would be another advancement in the art to improve the observability of intermediate stages in a partial scan environment. It would further be an advancement in the art to achieve the foregoing while maintaining the validity of the LBIST where scannable state elements that cannot tolerate random values are involved.
The present invention is generally directed to providing a pseudo partial scan design that operates as a full scan design and behaves like a partial scan design under particular test environments. A preferred embodiment of the present invention is embodied as a system that receives valid test responses from scan chains during a self-testing of Logic (LBIST). As referenced herein, a scan chain having only scan registers that can receive random data is referred to as a LBIST Random Scan Chain (LRSC) and a scan chain having one or more scan registers that cannot tolerate and cannot receive random data is referred to as a xe2x80x9cLBIST Non-random Scan Chainxe2x80x9d (LNSC).
A preferred embodiment of the system includes a psuedo-random pattern generator (PRPG) to generate random data signals having a plurality of bit values. The PRPG feeds the random data signals and bit values into one or more LRSCs having one or more scan registers. After passing the bit values through the LRSC, the LRSC feeds the bit values into the MISR. The system further includes one or more LNSCs having one or more scan registers that cannot tolerate random data. The LNSCs do not receive bit values from the PRPG but instead receive bit values from another scan chain. Before feeding bit values into a LNSC, the bit values are feed into a decoder and decoded. Thereafter, the LNSCs feed bit values into the MISR. The system may further include recirculation lines in electrical communication with LNSCs to recirculate original bit values back into the LNSCs. In an embodiment, the system further includes a 1-hot multiplexer having an input line that is in electrical communication with a scan register of a scan chain. The scan register that feeds the input line of the 1-hot multiplexer may be embodied as a series of successive state elements and inverters to ensure the 1-hot condition for the input line. An output line of the 1-hot multiplexer may be in electrical communication with a scan chain, such as a LRSC.
A preferred embodiment of the system may be described as having a scan path and a functional path. The scan path includes the PRPG, a scan chain (LRSC or LNSC), and the MISR. The functional path includes one or more scan registers, one or more decoders, the 1-hot multiplexer, and output functional logic.
In a preferred embodiment the system initializes the state elements within the scan registers of the LRSCs and the LNSCs. This performs a scan flush to initialize the state elements to a zero state. Prior to running the LBIST, the system may further temporarily disable clock input to state elements in the LRSC. The system may then perform a certain number of clock cycles to input partially decoded values into the state elements of the functional path. The process may then begin the LBIST process and feed random data to the LRSCs. Bit values are also decoded and feed into the LNSCs and then recirculated back into the LNSCs. Bit values outputted from the scan chains reflect test responses and are feed into the MISR which produces a signature. Bit values are further passed along the functional path into the 1-hot multiplexer.
The initialization process and structure of the system ensures that during loading of random data a 1-hot condition is maintained to the 1-hot multiplexer so as to prevent contention or a high current state. The present invention further improves observability of intermediate stages by preventing random data feeding of the LNSCs while allowing the LNSCs to feed the MISR.